Fin field-effect transistors (also called FinFETs hereinafter) are known as an alternative to customary field-effect transistor structures oriented in planar fashion in a semiconductor substrate with channel lengths of less than 100 nm. In the course of forming a FinFET, gate trenches are introduced into the semiconductor substrate in a recess step. In this case, a semiconductor fin is shaped from the material of the semiconductor substrate between two gate trenches in each case. Buried sections of a gate electrode (buried gate) are introduced into the gate trenches on both sides of the semiconductor fin. The buried sections of the gate electrode extend along the vertical sidewalls of the semiconductor fin. Besides the buried sections, the gate electrode comprises a section bearing on the semiconductor fin (top gate). The section of the semiconductor fin which is enclosed by the gate electrode on three sides corresponds to the channel region of the FinFET, at the first end of which a first source/drain region and at the second end of which a second source/drain region are formed in each case as a doped zone in the semiconductor substrate.
Depending on a gate voltage present at the gate electrode, a conductive channel is formed in the channel region between the two source/drain regions in the on state of the FinFET. In the case of the dimensions that are usually provided for FinFETs, the majority carries are virtually completely removed from the channel region even at comparatively low gate voltages. This means that, in the off state of the fin field-effect transistor, a parasitic charge carrier flow between the source/drain regions and thus a leakage current through the channel region are reduced. The channel width of the FinFET is determined by the depth of the gate trenches and is decoupled from the planar dimensions of the FinFET.
A method for fabricating fin field-effect transistors for DRAM memory cell arrangements is revealed in the publication “Fabrication of Body-Tied FinFETs (omega MOS-FETs) using Bulk Si Wafers”; Park et al.; in “2003 on VLSI Technology Digest of Technical Papers”.
A description is given below of a DRAM memory cell arrangement such as results from applying the method for fabricating FinFETs that is described therein to a DRAM memory cell arrangement having memory cells each having a trench capacitor for storing electrical charge and a FinFET as selection transistor for addressing the storage capacitor.
The trench capacitors and selection transistors of the memory cells are usually arranged either in chequered fashion in the manner of a “checkerboard layout” or in accordance with an “MINT layout” with—within the cell row—cell pairs of memory cells situated opposite one another in mirror-inverted fashion.
FIG. 1a and FIG. 1b show the resulting memory cell arrangements in accordance with a “checkerboard layout” and an MINT layout, respectively, in each case in a diagrammatic plan view, the illustration of overlying structures being dispensed with in part for the sake of better clarity.
A plurality of DRAM memory cells 2 are in each case arranged to form cell rows 63. A DRAM memory cell 2 in each case comprises a trench capacitor 3 and a FinFET 4 as selection transistor. An active zone 4′ of the FinFET 4 is formed in a semiconductor substrate and adjoins the respectively assigned trench capacitor 3 along a cell row 63.
The memory cells 2 are arranged in a manner offset with respect to one another in cell rows 63 that are respectively adjacent to one another. In the checkerboard layout of FIG. 1a, the offset between two adjacent cell rows 63 amounts to half the cell length of the memory cells 2 along the cell row. In the MINT layout in accordance with FIG. 1b, the memory cells 2 are arranged to form cell pairs within the cell rows 63, one of the two memory cells 2 in each case being rotated through 180° with respect to the other memory cell 2, so that the two memory cells 2 of the cell pair are situated symmetrically opposite one another within the cell row. The offset between two adjacent cell rows 63 in each case amounts to half the cell length of the memory cell 2 along the cell row 63.
The semiconductor substrate 1 is caused to recede between the cell rows 63, so that the memory cells 2 of respectively adjacent cell rows 63 are separated from one another by isolation trenches 61. Addressing lines 56 (also called word lines hereinafter) are provided in a direction perpendicular to the cell row 63. Each word line 56 is alternately led in sections as so-called passive word line over trench capacitors 3 and as active word line over the active zones 4′ formed in semiconductor fins 43. In the region of the isolation trenches 61, buried sections of the word line 56 mesh in comblike fashion between the cell rows 63. The overlying and buried sections of the word line 56 enclose a channel region within the active zone 4′ of the FinFET 4 on three sides. The two source/drain regions of the FinFET 4 are formed on both sides of the word line 56 in a manner adjoining the channel region within the semiconductor fin 43 as part of the active zone 4′. In this case, a first source/drain region adjoins a storage electrode of the trench capacitor 3 and a second source/drain region adjoins a bit line contact region 65 of the active zone 4′. Via the bit line contact region 65, the memory cell 2 is connected to a data or bit line that is to be provided above the word lines 56.
In the memory cell arrangement in accordance with FIG. 1b, the bit line contact region 65 is in each case jointly assigned to a cell pair of memory cells 2 formed symmetrically with respect to one another within the same cell row 63. The word line 56 is in each case alternately led in sections as passive word line over trench capacitors 3 and as active word line over the channel regions of the active zones 4′.
The word lines 56 are provided, by way of example, by a procedure in which, after the introduction of the isolation trenches 61, a conductive material is applied over the whole area and is patterned in a photolithographic method by means of a strip mask.
The word lines 56 meshing between the cell rows 63 in comblike fashion from above alternately enclose in each case a semiconductor fin 43 and an upper section of a trench capacitor 3 from three sides. A thin gate dielectric is provided between the semiconductor fin 43 and the word line 56.
If an insulator structure is provided between the word line 56 and the trench capacitor 3 in the same way as the gate dielectric, then this leads either to high parasitic coupling capacitances between the word line 56 and the trench capacitor 3 enclosed by the word line 56 or to reliability problems in the gate dielectric.
The document “Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM”; Katsumata et al.; in “2003 Symposium on VLSI Technology Digest of Technical Papers” describes a method according to which firstly the isolation trenches are introduced into the semiconductor substrate and only afterward are the trench capacitors formed. This ensures that the storage electrode respectively arranged in the interior of a trench capacitor is insulated from the word line by means of a collar insulator structure that is to be provided in a customary manner. It is disadvantageous that the method requires a processing that deviates significantly from the customary process implementation for trench capacitors, for instance since the introduction of the hole trenches or the formation of the trench capacitors is not based on a homogenous semiconductor substrate.